Thread: Integrated, memory controller

By modularizing the design of the CPU and the Northbridge, the memory controller has been brought to the Nehalem CPU die. The separate processing cores and caches are linked to the on board memory controller via a new bus standard called the QuickPath interconnect replacing the conventional front side. bus. As QuickPath replaces the Front side Bus (FSB), it also takes over the role of allowing the CPU to connect to other system components, buses and controllers such as the PCI Express controller and DDR3 memory, reducing latency and improving performance considerably.