- AMIBIOS ID string 40-0100-006156-00101111-080893-SIS461-P
- 8-30 pin SIMM slots (1-64meg FPM DRAM)
- 3-32bit VESA Local Bus slots
- 8-16bit ISA slots
- 64k-256k CACHE support in 8-28pin sockets + 1 TAG RAM
- AMI 1993 Auto-Detect BIOS or MR.BIOS
- Green PC Connector
- SiS 85C461 chipset
- Supports 3.3v/5volt CPU's
- ZIF 237pin CPU socket 3 which supports these processors:
INTEL 80486SX/SX2,80486DX/DX2/DX3, Pentium Overdrive
- Supports speeds of 20/25/33/40/50/66 MHz.
- Manufactured by: GENOA SYSTEMS
==View or Print jumper settings using Fixedsys or New Courier fonts==
GENOA TURBOEXPRESS 3-VL MOTHERBOARD
- Bios ID string 40-0100-006156-00101111-080893-SIS461-P
- 8-30 pin SIMM slots (1-64meg FPM DRAM)
- 3-32bit VESA Local Bus slots
- 8-16bit ISA slots
- 64k-256k CACHE support in 8-28pin sockets + 1 TAG RAM
- AMI 1993 Auto-Detect BIOS.
- Green PC Connector
- SiS 85C461 chipset
- Supports 3.3v/5volt CPU's
- ZIF 237pin CPU socket 3 which supports these processors:
INTEL 80486SX/SX2,80486DX/DX2/DX3, Pentium Overdrive
- Supports speeds of 20/25/33/40/50/66 MHz.
- Manufactured by: GENOA SYSTEMS
Connector and Jumper Settings
-----------------------------
The TurboExpress 486VL motherboard has two jumpers (JP7, JP6) for
the CPU type selector, and two jumpers (JP11, JP12) for the Cache Size
selection. Connectors are also provided for the front panel interface
between the system board and the computer chassis.
NOTE: JP2 and JP3 are used for the optional power saving feature on
the TurboExpress 486VL - 3G version.
Front Panel Speaker Connector (JP15)
------------------------------------
Connector JP15 is a 4-pin single in-line BERG strip which provides
a front panel speaker connection. The pin assignments are:
JP15 Pin# Assignment
1 Speaker Data
2 N.C.
3 Ground
4 +5 V
Front Panel Keylock / Power LED Connector (JP16)
------------------------------------------------
Connector JP16 is a 5-pin single in-line BERG strip which provides
a front panel keylock and power LED connection. When it is connected
to a lock on your system case, you can enable or disable the keyboard
by switching the key. The pin assignments are:
JP16 Pin# Assignment
1 LED Power
2 N.C.
3 Ground
4 Keyboard Inhibit
5 Ground
Front Panel Reset Connector (JP17)
----------------------------------
The reset button connector is a 2-pin single in-line BERG strip.
It is used to reboot the system and will allow safe re-initialization
of the system at any time. The connector should always be set in the
OFF position, otherwise the system will continually reset itself.
JP17 Pin# Assignment
1 Ground
2 Reset Strobe
Front Panel Turbo LED Connector (JP18)
--------------------------------------
Connector JP18 is a 2-pin single in-line BERG strip. It can be
connected to an LED display indicating the CPU speed. The display
lights up when the CPU is running at full speed.
JP18 Pin# Assignment
1 Anode
2 Cathode
Front Panel Turbo Connector (JP19)
----------------------------------
Connector JP19 is a 2-pin single in-line BERG strip. It is the
connector for the 'Turbo' processor speed switch, which allows you
to switch between system speeds.
JP19 Pin# Assignment
1 Ground
2 Turbo Control
Hardware CMOS Setup Connector (JP21)
------------------------------------
The hardware CMOS setup Connector is a 3-pin connector.
To discharge the CMOS static memory (clear the CMOS setup settings),
remove the jumper shunt from pin 2 and 3 of JP21 (default setting),
and place it at the position of pin 1 and pin 2 of JP21 for 5 seconds,
then return it ot the original position. The jumper selections are:
Selections JP21
Default 2-3
Discharge 1-2
Power Supply Connector (PW1)
----------------------------
There is a power supply connector on-board. The pin assignments are:
PW1 Pin# Assignment PW1 Pin# Assignment
1 Power Good 7 Ground
2 +5 VDC 8 Ground
3 +12 VDC 9 -5 VDC
4 -12 VDC 10 +5 VDC
5 Ground 11 +5 VDC
6 Ground 12 +5 VDC
Cache Memory Configuration
--------------------------
There are two jumpers to be set for the cache memory selection.
For 64K cache, install 8Kx8 SRAM in locations
U27, U23, U24, U25, U26, U33, U34, U35, and U36.
For 128K cache, install 8Kx8 SRAM in location U27,
and 32Kx8 SRAM in locations U23, U24, U25, and U26.
For 256K cache, install 32Kx8 SRAM in location U27,
and 32Kx8 SRAM in locations U23, U24, U25, U26, U33, U34, U35, U36.
Selection JP11 JP12
64K Open Open
128K 1-2 Close
256K 2-3 Close
External Battery (JP1)
----------------------
The TurboExpress 486VL motherboard provides one external battery
supply connector. The pin assignments are:
JP1 Pin# Assignment
1 Battery Positive
2 No Connection
3 Ground
4 Ground
Keyboard Connector (KB1)
------------------------
The keyboard connector is a 5-pin DIN connector. This connector
consists of a 90-degree printed circuit board PCB mounting.
KB1 Pin# Assignment
1 Keyboard Clock
2 Keyboard Data
3 Spare
4 Ground
5 +5 V
CPU Type Selection
------------------
The TurboExpress 486VL motherboard can accommodate either
the Intel 486DX, 486DX2, 486DX3, 486SX, 487SX, 486 OverDrive,
or Pentium OverDrive. There are two jumpers to be set for the
microprocessor selection. Configuration of the correct CPU
setting will allow compatibility with various low-end and high-end
applications. The jumper settings are:
CPU Type JP7 JP8
486DX/486DX2/486DX3 1-2,3-4 1-2
486 OverDrive 168-pin 1-2,3-4 1-2
486 OverDrive 169-pin 1-2,3-4 2-3
Pentium OverDrive 1-2,3-4 2-3
486SX 2-3 Open
487SX/486SX2 1-2,3-4 2-3
CPU Clock Selection
-------------------
The TurboExpress 486VL motherboard uses a CPU frequency generator
to generate the clock instead of an oscillator. There are three
jumpers to be set for the CPU clock selection.
CPU Clock JP4 JP5 JP6
DX-50 MHz Open Close Open
DX-40 MHz Close Open Open
DX-33/DX2-66 MHz Open Close Close
DX-25/DX2-50 MHz Close Open Close
DX-20 MHz Close Close Open
VESA Local-Bus Identifier Jumpers (JP13, JP14)
----------------------------------------------
The identifier jumpers (JP13, JP14) allow the VL-Bus slave to
identify the speed of the host CPU.
CPU Speed JP13 JP14
<= 33 MHz Open Open
> 33 MHz Close Close
===================End of Genoa TurboExpress VL Data====================
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