Thread: Circuit description

shows the circuit of sequential power'on.' It comprises opto coupler 4N33, divide¬by-12 counter CD4040, divide-by-16 counter 74LS93, 1-of-16 decoder 74LS154, setrest flip-flop(s) 74LS74, NAND gate(s) 74LSOO, regulator 7805 and a few discrete components. AC mains operating frequency is 50 Hz, which is isolated through optocoupler 4N33. shows the pin configuration of 4N33 and BC337.

Optocoupler 4N33 consists of a gallium-arsenide infrared LED and a silicon photo-Dar¬lington transistor. AC mains is connected to pin 1 of 4N33 via current-limiting re¬sistor R3. During the positive half cycle, the internal LED of 4N33 is 'on' and the pho¬to transistor is driven into saturation and pin 5 goes low. Thus 4N33 provides clock for CD4040 at pin 10.

The CD4040 is a 12-stage ripple carry binary counter. The counter advances by one count on the nega¬tive transition of each clock pulse. It resets to zero with a logical high at the reset input, independent of the clock. Each counter stage is a static toggle flip-flop. Counter CD4040 further divides the 50Hz clock frequency by '10.' Output pin 14 provides clock pulse after an interval of 20.48 sec¬onds and also drives 74LS93.

The 74LS93 is a 4-bit binary ripple counter. It consists of four master-slave flip-flops internally connected to pro¬vide a divide-by-two section and a divide-by-eight section. Each section has a separate clock input (CPO and CP1) to initiate state changes of the counter on the high-to-low clock transition. A gated AND asynchronous master reset (pins 2 and 3) is provided, which resets all the flip-flops.

Since the output from the divide¬by-two section is not internally con¬nected to the succeeding stages, in a 4-bit ripple counter the QO output must be externally connected to CP1 input. The input count __ Eulses are applied to clock input CPO. Simul¬taneously, frequency divisions of 2, 4, 8 and 16 are performed at the QO, 61, Q2 and Q3 outputs, respectively. The outputs of 74LS93 provide the address inputs to 1-of-16 decoder 74LS154.



The decoder 74LS154 accepts four active-'high' binary address inputs AO through A3 and provides 16 mutually exclusive active-'low' outputs 00 through 015. The EO and E1 inputs enable the gate, which can be used either to strobe the decoder for eliminating the normal decoding glitches on the outputs, or for expansion of the decoder. The enable gate has two AND' ed inputs which are made low (by connecting them to ground) to enable the outputs. Outputs 00 through 015 of 74LS154 are connected to the set inputs of flip-flop 74LS74.

rC5 through rC12 (each 74LS74) are used as set-reset flip-flops to drive the relays with the help of transistors T1 through T16. The 74LS74 is a dual, positive-edge-trig¬gered, D-type flip-flop featuring individual data, clock, set and reset inputs and also true and complementary outputs. Set input'S' and reset jnput 'R' are asynchronous active-'low' inputs that operate independently of the clock input. When reset input 'R' is high and set input 'S' is low, the 'Q' output goes high to energise the relay.

The 'Q' outputs of 74LS74 rcs are