If there is one thing we wish about attending IDF it is that we commonly walk away familiar fairly much all about a following-gen Intel central processing unit - from its architecture, by Intel's innovations to dilute its power draw, and still how to overclock the nuts off it. This is the case with Ivy Bridge, Intel following-generation LGA 1155 central processing unit family, which we look to see in March or April of 2012.
There is been rather a bit of data already freed about Ivy Bridge to get up the excitement levels, so we will recap entire that early diving into the fresh learnings and their practical implications.
Ivy Bridge will be the beginning commercial central processing unit to utilize Tri-Gate transistors, and too the beginning to utilize a 22nm manufacturing function. We will take over Professor Kelin Kuhnís explanation of a Tri-Gate transistor (chiefly because it is the first explanation we truly realize ourselves). The simplest way to imagine of a Tri-Gate transistor is to think a typical transistor as a piece of paper; squish the 2 sides of it and the middle bows up in the center, and that is a 3D transistor, as you can see in the picture below.
However, in a trio-Gate transistor, the channel is in three dimensions, meaning that the dielectric above this is too in three dimensions. As electricity can flow around entire 3 sides of the channel, this is a neat way of diluting transistor size on the silicon die (to the width of the fin), when maintaining a sufficiently long gate length for a powerful signal.