Digital Logic Overview

1. Digital logic, building blocks of all new electronics, depend on work of individual electronic switches being in either an on or off situation. These switches are grouped together into logic gates which work as said by identified rules.

Logic states are usually referred to as either high or low, equivalent to two states of a switch (ON and OFF).

Amongst most common of logic gates NOR gates, which will output a logic low state for every input condition except when both inputs are logic low. Two low logic inputs to a NOR gate produce a logic high output.

Latch Operation

2. Digital latches are amongst most common building blocks of new electronics, and new microprocessors have millions of these devices.

Easiest kind of flip-flop is called set/reset (SR) type. It is, in essence, a one-bit memory. There are many other kinds of flip-flop, contain delay (D), toggling SR (JK) and toggling (T). There are many other variations.

Flip-flops are utilized for a wide range of uses generally to remember a particular bit of data as remainder of circuitry is executing another task.

Theory and Construction

3. An SR flip-flop has two inputs, SET and RESET with two outputs, Q and Q_BAR. Q_BAR is forever in opposite logic state of Q.


The usual operation occupies both inputs being held in a low state, and then a pulse applied to SET input. This will cause Q output to go to a high state, and stay that way after end of pulse. Equally, if both inputs are held low and a pulse is applied to RESET input, Q output will go to a low state.

To explain it another way, a pulse on SET line will put Q output into a logic high state. The Q output will stay in a logic high state until RESET line gets a pulse. RESET pulse will place Q output into logic low state until next SET pulse arrives.


Q output will "flip-flop" as irregular SET and RESET pulses are applied, so earning device its usual name.


Theory and Construction

4. SR filp flop builds from two NOR gates. The SET and RESET line are one input to every NOR gates, as second input is output of other NOR gate.

As a high logic level is there on SET input, output of first NOR gate is low logic level, as high state NOR with something forever effects in a low state. This low signal is fed to input of second NOR gate, where it causes output of NOR gate to go to a high state. This high state, output, when fed back to an input of primary NOR gate successfully locks that gate into a low output. Now Q output is in high state, and flip flop is in a mode where only a high input to second NOR gate can cause a modification. A high input to RESET input will now reverse earlier operation, causing Q output to go low.