SoCs at 32nm node Panasonic and Renesas Technology are developing elemental process technologies for systems-on-a-chip (SoCs) of the next-generation 32nm node. The two companies are confident that their 32nm node transistor technology and other advances can soon be applied to products in mass production. It is anticipated that SoCs at the 32nm node will deliver lower cost and improved performance enabled by miniaturisa¬tion of their design rules.The new 32nm SoC process employs a transistor technology with a metal/high-k gate stack structure and interconnect, using an ultra-Iow-k material.
To achieve a device using com¬plementary metal-insulator semi conductor at a 32nm node, an ultra-thin film cap layer is applied at the atomic level to transistors with a metal/high-k gate stack structure under optimised conditions. This enables development of a conventional transistor configuration, which allows the use of an oxi¬dised silicon film as the gate insulation layer. The introduction of the cap layer has been shown to improve transistor reliability in practical use and suppress distribution of electrical characteristics between transistors, thereby enabling the operation of large-scale circuits. The latest development on the 32nm fabrication process will be applied to SoCs for advanced mobile and digital home appliance products.
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