Tilera has currently declared the latest TILE-Gx100, which is the world’s foremost 100-core CPU. The TILE-Gx100 is in fact part of the company’s TILE-Gx family, additional three CPUs in the family have 16, 36 as well as 64 cores.

The Tilera TILE-Gx is being supported on an exclusive structural design that scales well ahead of the core count of usual microprocessors. Tilera’s two-dimensional iMesh intersect eliminates the necessitate for an on-chip bus along with its Dynamic Distributed Cache (DDC) system enables every cores’ local cache to be shared logically across the whole chip. The TILE-Gx family also elevates the bar for performance-per-watt to innovative levels with ten times superior compute efficiency compared to Intel’s future generation Core i7 (aka Westmere/Nehalem) CPU.

Tilera’s TILE-Gx, is being made-up in TSMC’s 40nm development, which runs at a speed of up to 1.5 GHz with power utilization varying from 10 to 55 watts. With several expertise highlights:

• Next-generation 64-bit core: With new-fangled three-issue 64-bit core with complete virtual memory system. Every core contains 32KB L1 I-cache, with 32KB L1 D-cache as well as 256KB L2 cache, with up to 26MB total L3 coherent cache across the device.

• Improved SIMD instruction extensions: Highly developed signal giving out act with a 4 MAC/cycle multiplier component distributing up to 600 billion MACs for each moment, more than 12x the best ever commercial DSP.

• Built-in high-performance DDR3 memory controllers: Two or else four 72-bit controllers working at speed of up to 2133 MHz speeds with ECC support. Up to 1TB total capability as well as influential memory striping modes for maximum operation.

• Hardware acceleration engines: On-chip MiCA (Multistream iMesh Crypto Accelerator) system convey up to 40Gbps encryption with 20Gbps full duplex compression dispensation, forcefully fixed to the iMesh for tremendously low latency with wire-speed small packet output. As well, a high-performance true random number generator (RNG) along with public key accelerator allow up to 50,000 RSA handshakes for each moment.

• Packet processing accelerator: mPIPE (multicore Programmable Intelligent Packet Engine) system also offers wire-speed packet categorization, which load balancing with buffer running. This feasible, C-programmable engine conveys 80 Gbps along with 120 million packets-per-second of output for packets with numerous layers of encapsulation.

The TILE-Gx36 CPU will be example in Q4 of 2010 with the additional CPUs rolling out in the next two quarters.