Now XDR will shine. The intense overclockers combining top of PC parts can push memory bandwidth to 9.0 GB/sec. Most people won’t be seeing this type of performance until end of DDR2 or later. XDR will launch at 9.6GB/sec, and current highest is 16GB/sec with higher on prospect.

The main objection about DDR2 is their latency. Latency plays a main role in bandwidth. DDR has a latency of about 10 ns, while DDR2’s latency is closer to 15ns. This is why DDR beats DDR2 at similar speed. XDR's latency will be lower than that of DDR. It will be available in latencies of 1.25/3.0/2.5/3.33 ns. This will give an extra advantage over DDR2. The clocks must stay on par with DDR2, but when XDR is clocked to higher speeds the gap will increase.

FlexIO

Rambus has made a latest technology known as FlexIO; it is prepared by couple of parts, FlexPhase and DRSL.

FlexPhase will permit specific on-chip alignment of data with clock. This does not mean a lot to consumers as it does motherboard companies. The companies do not want to be worried about PCB trace lengths matching and PCB timing constraints. Even surprise why you look at motherboards the traces looks to run in funny patterns?

This is because present memory technologies want whole tracer lengths from memory to memory controller wants to be similar length. If all tracers are similar length, then each bit of info will arrive in right order. If the tracers are various lengths, data with shorter route will obtain there faster then data from a longer tracers. For customers means that motherboards can be much simpler, thus smaller, and maybe cheaper.

Differential Rambus Signaling Levels (DRSL) is another part of FlexIO. The full idea of PC advancement is to obtain the parts faster and cooler. The fastest method of cooling it down is decreasing voltage. Generally lower voltage becomes harder it is to distinguish between electrical “high” and “low”; it is easier for PC to tell difference between 3.0 volts and 0 volts then .09 volts and 0 volts. DRSL will utilize difference between two voltage lines with a little voltage difference and use that difference for its signaling. This means overall memory voltage and be decreased to about 1.8 volts.