Is it possible to offer a compatible x86 processor without possessing a license, while keeping performance correct? China seems to think so. Indeed, the next CPU Longsome family - the Godson-3 - propose a system of support that will help provide support in the x86 emulator with support in hardware.

Godson-3

The Godson processors are 64 bit based on the MIPS architecture, an instruction set fairly common in the embedded world. The Godson-3, which will be produced in 65 nm by ST-Micro is a processor with four cores, using a HyperTransport bus (such as AMD) and is equipped with 4 MB of L2 cache (1MB per core ). Clocked between 1 and 1.2 GHz, 10 W for consumption, this processor seems efficient. And what interests us, it will be able to speed up the emulation of x86 instructions, which avoids paying a license (and to create from scratch a x86 processor) while maintaining proper performance.

An assisted emulation

The idea is simple: a full software emulator is generally slow, the instruction sets of different architectures are often very different, especially the FPU. And x86 is a complicated instruction set to emulate the one hand by its CISC legacy and its multiple variations, partly because of its atypical FPU on x87. To give an idea, an example is given: a code of 2 assembler x87 instructions should be processed normally, in 22 MIPS instructions. Even if the latencies are obviously not identical, we realized that the transformed version for MIPS must pose performance problems. The idea of Chinese engineers is to delegate a part of processing the processor itself. Without going into detail, four techniques are used. The first is to manage the operation in hardware in the x87 stack and thus significantly speed up the calculations on the FPU. Some specific exceptions seem to run in software, but the whole remains a priori faster than just emulation. Second point, a unit is able to accelerate some x86 instructions in the decoding directly. Typically, these are basic instructions that are common to most processors, and which only the syntax changes depending on the instruction set. The third is to basically make the branch prediction materially assisting the emulator to correctly handle the connections. The final optimization can easily switch from one program in MIPS instruction set with a program "x86 emulation" so fast with such a system quickly to save the records.

Proper performance

According to preliminary tests (performed on FPGA versions and simulators), an x86 code running on a Godson-3 in a conventional manner (with a fully software emulation) offers about 20% of native performance while the same program run with the aid material achieves approximately 70% of native performance. By means native performance comparison between a program compiled into MIPS and running on the Godson-3 and the same program compiled on the x86 Godson-3. The problem will be twofold: the tests are currently performed on a FPGA (programmable chip) clocked at 50 MHz (performance was then extrapolated to a Godson to 1 GHz) and will require that the Godson-3 in native is efficient. A problem that is not a priori one, the Godson-2 processor is about right, especially for a second test.

In fact, we must realize one thing: this processor is designed for the Chinese market and it is unlikely that he landed on a massive scale in the West. Recall that the Godson-2, a success in China, is available only anecdotally in our country (via a netbook Emtec).