At the annual conference of the International Solid State Circuits Conference (ISSCC), which is traditionally held in February in San Francisco, Intel and Advanced Micro Devices will present some documents about the next generation of processors that will be produced on 32nm process technology. Among the multi-core architectures, which will be discussed at this event, will also IBM Power7 and Sun Microsystems Rainbow Falls.

Compared with other manufacturers of Intel processors, the company has a big advantage, because it will tell on the ISSCC of the family of 32nm Westmere. Dual-core model, made of finer process technology, will significantly reduce chip size compared to existing models of Intel Nehalem. Server-six-core processor, made on 32nm process technology, will appear on the market until June, said Nathan Brookwood (Nathan Brookwood), Rector of Insight64 (Saratoga, CA). Six-core processors Intel Westmere, which will be described in a paper presented at ISSCC, will have 1.17mlrd transistors, use 12Mb total L3 cache and support low-voltage memory DDR3. The paper also describes the new anti-resonance function interface QuickPath Interconnect, which reduces interference.

In 2010, AMD will be releasing a series of 45nm processors, including Magny Cours, which will be processor, "hired by" two six-core and intended for servers. In its report on the ISSCC AMD will release its plans for 2011 and talk about future 32nm AMD processors, the core of which will operate at a frequency of 3GHz and have more power in the range of 2.5Vt up to 25 watts. While not entirely clear on what exactly the core question, as it is rumored that next year the manufacturer will present two new 32nm models, as well as transfer to the 32nm process technology, some existing models. AMD also intends to focus on the method used for low power consumption and leakage. For example, L1 cache uses memory cell 8T to support low-voltage power supply. The chip also uses a special insulating ring, which, due to isolated substrate, created by the technology of silicon-on-insulator, provides virtually zero power consumption in the off state.

In addition to the processors and related technologies digging Intel will present papers describing research on three different types of on-chip networks, which it could use in future multicore chips. One of the devices created by the researchers is built on 45nm process technology and use 48 x86 cores in 6x4 network. It uses a scheme of communication with built-in shared memory for implementing virtual networks with cross-cutting capacity 256 GB / s. A separate document will describe an experimental stream-switching network protocol, which will be applied to the 64-node on-chip network, supporting the overall network bandwidth 2.6Tbit / sec. The third paper will describe the research ring bus, which provides bandwidth 1.2Tb / s between the eight-core chips Xeon.

In turn, IBM will present two papers on the implementation of its 45nm architecture of Power, using built-in DRAM. In one version will use eight cores Power7, the latter architecture company, describe in August at a conference Hot Chips? In the other version uses 16 cores of unknown Power Generation together with accelerators responsible for the safety and networks. Company Sun Microsystems will describe on their chip, Rainbow Falls, which uses 16 cores supporting eight threads each, and placed on 40 nm process technology. This processor also initially was described in the Hot Chips.