Soitec and CEA-Leti have teamed up to develop chips piling dies on each other.

Wafer-to-wafer

The technologies developed will focus on wafers of 200 mm and 300 mm will reduce component size and consumption, while increasing their performance. Instead of enlarging the surface of the chip, engineers are trying to stack the dies by connecting using copper links. In practice, this will, inter alia, to increase the capacity of memory chips for example.

Partnership

Specifically, Soitec bring its Smart Stacking, which enables an architecture 3D wafer-on-wafer processes and cuts, while CEA-Leti is an important player in the development of techniques to assemble and link the layers together.