Today chipsets are without VIA KT/PX series and SiS 746/648, are by one type of "dual channel" memory. These two times data rate attached with moves of bits from memory to memory controller in North Bridge. To describe this, consider a highway. When full with cars, they can all travel at similar speed, and you can't make any more cars fit throughout, without increasing that speed. If you extend that highway. Make it in two as wide and now double as many cars can travel on it. This is finished by including another memory controller to North Bridge, and having an algorithm attach them together. DDR SDRAM works with a 64 bit bus, so including two obtain you a 128 bit combined bus.

For platform dependant part, consider a highway but this time a 4 lane wide one, indicating a dual channel DDR configuration. Now assume that highway comes up to a bridge. If that bridge is also 4 lanes across, then there is no sour off of the data, it can all ramp easily onto and over bridge. This is what happens in an Intel Pentium 4 configuration. That bridge is FSB. Because a P4's FSB is "quad pumped" for data, it is able of bringing all that data from 128bit channels right in. What "quad pumped" means, is same to DDR developments. Only this time, data is sent twice on increasing and falling edges. Imagine that signal voltage is 1.5V. When voltage reaches 0.7V, data is sent, and again when 1.5V is reached. On down slope, similar thing happens, data sent at 0.7V and 0V. This describes why P4 architecture is like bandwidth control. When using a single memory controller configuration, such as i845 chipset, or an i865/i875 with only one channel being used, FSB is able of sending much more data than memory controller can bring in from ram, causing incompetence.

This condition is rather opposite for a system depends on Athlon XP architecture. Again, consider of our 4 lane highway, indicating a dual channel DDR configuration. This time however, our bridge is only 2 lanes wide. This is because Athlons' FSB is only able of DDR equivalent performance. So that second channel goes to waste, as you cannot force all cars through bridge immediately. The only time this comes in helpful is when latencies reduce RAM from performing as fast as FSB is capable of taking in data.